1. Field of the Invention
The present invention relates to a lead on chip (LOC) type semiconductor memory device.
2. Description of the Related Art
An LOC assembling technology, which can mount a large size chip on a small package, has been broadly used in 16 Mbit dynamic random access memory (DRAM) devices or the like.
In a first prior art semiconductor memory device including two rows, two columns of memory cell arrays, a data input/output circuit including its pads and control signal pads are arranged between one column of the memory cell arrays, and address signal circuits including their pads are arranged between the other column of the memory cell arrays. This will be explained later in detail.
In the above-described first prior art LOC type semiconductor memory device, however, bonding wires for connecting data input/output pads, control signal pads and address signal pads to their leads (or pins) cross a power supply lead or a ground lead. As a result, the data imput/output leads, the control signal leads and the address signal leads may be short-circuited to the power supply lead or the ground lead.
In order to avoid the above-mentioned short circuit between the leads, in a second prior art semiconductor memory device including two rows, two columns of memory cell arrays, a data input/output circuit including its pads and control signal pads are arranged outside of one column of the memory cell arrays, and address signal circuits including their pads are arranged outside of the other column of the memory cell arrays. This will also be explained later in detail.
In the above-described second prior art LOC type semiconductor memory device, however, since the control signal pads are separated, at two locations, the control signal circuit has to be located at the center of the control signal pads. As a result, a signal path between the data input/output circuits and the control signal pads via the control signal circuit is so long that it increases an access time.